1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a floating gate type non-volatile semiconductor memory device having two-layer gate electrodes of a floating gate electrode and a control gate and a method for fabricating it.
2. Description of a Related Art
In recent years, low-cost and large-capacity non-volatile semiconductor memory devices have been used. In order to provide such non-volatile semiconductor memory devices widely, a structure which can be easily micro-structured and its manufacturing method have been demanded.
Now, referring to step sectional views of FIGS. 19 to 26, an explanation will be given of a method of manufacturing a conventional semiconductor memory device.
In FIGS. 19 to 26, reference numeral 1 denotes a semiconductor substrate; 2 an element isolation insulating film; 3 a gate insulating film; 4 a floating gate electrode; 5 a floating gate electrode processing mask; 6 a gate electrode interlayer insulating film; 7 a control gate electrode; and 8 a control gate electrode processing mask.
First, a relatively thick element isolation insulating film 2 is selectively formed on a semiconductor substrate 1. On the surface of a region of the semiconductor substrate 1, not covered with the element isolation insulating film 2, a gate insulating film 3 is grown. Thereafter, on the element isolation insulating film 2 and gate insulating film 3, a floating gate electrode 4 is grown (FIG. 20). On the floating gate electrode 4, a floating gate electrode processing mask 5 having a prescribed pattern is formed, and thereafter the floating gate electrode 4 is patterned into a prescribed pattern (FIG. 21). After the floating gate electrode processing mask 5 is removed, on the floating gate electrode 4, element isolation insulating film 2 and an exposed area of the gate insulating film 3, a gate electrode interlayer insulating film 6 is formed, and a control gate electrode 7 is formed thereon (FIG. 22). On the control gate electrode 7, a control gate electrode processing mask 8 having a prescribed pattern is formed (FIG. 23). Further, using the control gate electrode processing mask 8, the control gate electrode 7 is processed in a prescribed pattern (FIG. 24). Exclusive of a part of the gate electrode interlayer insulating film 6 just below the patterned control gate electrode 7 and portions of the gate insulating film 3 and element isolation insulating film 2, the remaining area of the gate electrode interlayer insulating film 6, the floating gate electrode 4, the gate insulating film 3 and element isolation insulating film 2 is selectively removed (FIG. 25). After part of the floating gate electrode 4 and semiconductor substrate 1 are removed, the control gate electrode processing mask 8 is removed (FIG. 26).
Referring to step sectional views of FIGS. 27 to 37, an explanation will be given of another method of manufacturing a conventional semiconductor memory device. This method is a method of manufacturing a semiconductor memory device having a pattern shown in a plan view of FIG. 1. In each of FIGS. 27 to 37, the views (X1) on the left side correspond to the portion along line X1--X1 in FIG. 1, whereas the views (Y) on the right side correspond to the portion along line Y--Y in FIG. 1.
In FIG. 27 to 37, reference numeral 9 denotes an implanted region for controlling a threshold value; 10 a source/drain implanted region; 11 an offset region, 12 a substrate dig-preventing insulating film; and reference numerals 1 to 8 refer to like elements in the step sectional views of FIGS. 19 to 26.
First, an implanted region 9 is formed on the one principal surface of a semiconductor substrate 1 by ion implantation (FIG. 27). After a gate insulating film 3 is formed on the implanted region, a floating gate electrode 4 is grown thereon (FIG. 28). A floating gate processing mask 5 having a prescribed pattern is formed on the floating gate electrode 4. Using the floating gate electrode processing mask 5, the floating gate electrode 4 is processed in a prescribed pattern (FIG. 29). By slanted ion implantation, a source/drain implanted region 10 and an offset region 11 are formed in the implanted region 9 (FIG. 30). The floating gate electrode processing mask 5 is removed and a substrate digging preventing insulating film 12 for preventing substrate from being dug is grown on the floating gate electrode 4 and gate insulating film 3 (FIG. 31). The entire substrate digging preventing insulating film 12 is removed to such a thickness as the upper face of the floating gate electrode 4 is exposed and the insulating film 12 is also left on the semiconductor substrate (FIG. 32). A gate electrode interlayer insulating film 6 is grown on the floating gate electrode 4 and substrate digging preventing insulating film 12, and a control gate electrode 7 is formed thereon (FIG. 33). A control gate electrode processing mask 8 having a prescribed pattern is formed on the control gate electrode 7 (FIG. 34). Further, using the control gate electrode processing mask 8, the control gate electrode 7 is processed in a prescribed pattern (FIG. 35). Exclusive of areas of the gate electrode interlayer insulating film 6 and substrate digging preventing insulating film 12 which are just below the patterned control gate electrode 7, the other area is removed (FIG. 36). After the floating gate electrode 4 is selectively removed, the control gate electrode processing mask 8 is removed (FIG. 37).
Referring to FIG. 38, an explanation will be given of an example of a conventional semiconductor memory device. In FIG. 38, the view (X2) on the left side is a sectional view taken along line X2--X2 in FIG. 1, whereas the view (Y) on the right side is a sectional view along line Y--Y in FIG. 1. In FIG. 38, like reference numerals refer to like elements in FIGS. 19 to 26 and FIGS. 27 to 37.
In this device, the source/drain implanted region 10 and offset region 11 are formed by slanted ion implantation so that an asymmetrical source/drain structure is realized. In this case, the source of a floating gate electrode 4a is a source/drain implanted region 10a and the drain thereof is a source/drain implanted region 10b. The source of the floating gate electrode 4b is a source/drain implanted region 10b and the drain thereof is a source/drain implanted region 10c.
This device operates in a virtual grounding system in which the same diffused layer is a source or drain according to the corresponding floating gate electrode 4.
A written state can be obtained in such a manner that with the control gate electrode 7 supplied with -10V, drain supplied with 3 V, source placed in a floating state and semiconductor substrate 1 placed in a grounded state, electrons are extracted from the floating gate 4 to provide a threshold voltage of about 1 V.
An erased state can be obtained in such a manner that with the control gate electrode 7 supplied with 12 V, and drain/source and semiconductor substrate 1 in a grounded state, electrons are implanted into the floating gate electrode 4 to provide a threshold voltage of about 4 V.
At the time of reading, the control gate electrode 7 and drain are supplied with 3 V and 1 V, respectively, and source and semiconductor substrate 1 are placed in the grounded state. Then, in the written state where the threshold voltage is about 1 V, a current flows from the drain to the source. On the other hand, in the erased state where the threshold voltage is about 4 V, no current flows from the drain to the source. By detecting such a current difference, the written state and the erased state can be discriminated from each other.
The performance of the non-volatile semiconductor memory device can be evaluated in terms of a capacitive coupling ratio CR. Assuming that the capacitance between the floating gate electrode 4 and control gate electrode 7 is Cp and that between the floating gate electrode 4 and semiconductor substrate 1 is Cox, the capacitive coupling ratio CR can be expressed by the following equation (1) EQU CR=Cp/(Cp+Cox) (1)
Generally, the larger the value of the capacitive coupling ratio CR is, the better the performance is. However, the product which is actually available has a standard value of CR=0.60.
In FIG. 38, assuming that the width of the floating gate electrode 4 is 0.3 .mu.m, height of the floating gate electrode 4 is 0.3 .mu.m, height of the area covered by the gate electrode interlayer film 6 on the side of the floating gate electrode 4 is 0.15 .mu.m, thickness of the gate insulating film 3 is 7 nm and thickness of the gate electrode interlayer film 6 is 14 nm, EQU CR=0.50
This value is smaller than the standard value of CR=0.60.
However, the conventional manufacturing method, in which the area corresponding to the region where the floating gate electrode is removed is dug by over-etching as shown in FIG. 12d, has problems in reliability such as generation of a leak current and in manufacturing of a semiconductor memory device. In order to prevent the semiconductor substrate from being dug, the region where the floating gate electrode is to be removed must be formed on a relatively thick insulating film such as an element isolation insulating film, or the relatively thick insulating film must be embedded in the region where the floating gate electrode has been removed. There are still problems when realizing the microstructure of the semiconductor memory device and easiness of the manufacturing method.
The present invention intends to solve the problems, and to provide a method for manufacturing a semiconductor memory device which can prevent a semiconductor substrate from being dug without forming a region where a floating gate electrode is to be removed on a relatively thick insulating film, or otherwise embedding the relatively thick insulating film into the region where the floating gate electrode has been removed.
In the conventional semiconductor memory device, in which a portion of the side wall of the floating gate is only covered with the gate electrode interlayer insulating film, a sufficiently large capacitance between the gate electrodes cannot be obtained so that the capacitive coupling ratio necessary in operation cannot be obtained.